The invention relates to a device and a process for heat treating (also referred to as annealing) of III-V wafers (also called substrates), and to annealed wafers or substrates. The invention particularly relates to the aforementioned device, process and wafer based on GaAs semiconductor materials, above all of semi-isolating (SI) GaAs wafers, as well as GaAs wafers produced according to the VGF (Vertical Gradient Freeze) and the VB (Vertical Bridgman) process. Because the electric, electronic and other physical properties of such annealed wafers are adjustable, they are particularly suited for the manufacture of active microelectronic devices based on III-V semiconductors.
In the crystal growth process from a melt, the solidified material goes through a thermal history dependent of location. That is, the effective maintenance time in a certain temperature range, in which balancing or compensation processes (e.g. relaxation of residual strength, homogenization, etc.) are possible, varies for different parts of a crystal. Therefore, it is common practice to subject single crystals to an equational heat treatment after the termination of the crystal growth process, either in the growth apparatus or preferably in a separate heating furnace. The annealing of GaAs single crystals was first applied by RUMSBY et al. (D. Rumsby, R. M. Wafer, B. Smith, M. Tyjberg, M. R. Brozel, E. J. Foulkes: Tech. Dig. GaAs IC Symp., New York, IEEE, 1983, 34) for strain relaxation and homogenization of electrical properties of non-doped, semi-insulating LEC Liquid Encapsulated Czochralski)-GaAs single crystals. Since then, the crystal annealing processes have been systematically optimized, specifically with respect to the application and the customer; and in addition to homogenization, they also serve for the control of defect sites. An overview of crystal annealing of GaAs is given, inter alia, by ODA et al. (O. Oda, H. Yamamoto, K. Kainosho, T. Imaizumi, H. Okazaki: “Recent developments of bulk III-V materials: annealing and defect control,” Inst. Phys. Conf. Ser. No 135, pp 285-293, 1993).
The basic physical mechanism of each heat treatment is the diffusion of intrinsic defect sites and impurities under the consideration of possible factors, such as Fermi level and dislocations, which possess increased diffusibility (“pipe diffusion”) and with which point defects may react (segregation). Due to the smallness of the self diffusion coefficients and many extrinsic diffusion coefficients even close to the melting temperature of GaAs, the equational processes affected thereby are limited to mesoscopic linear dimensions (O(100 μm)). In particular, a homogenization of axial and radial concentration inhomogeneities, which are formed by macrosegregation of dopants and impurities during crystal growth, is not possible by crystal annealing.
Specifically, GaAs has a homogeneity region that includes the stoichiometric composition, with a retrograde solubility at least on the As-rich side of the homogeneity region (H. Wenzl, W. A. Oates, K. Mika: “Defect thermodynamics and phase diagrams in compound crystal growth processes,” in: D. T. J. Hurle (ed.): Handbook of Crystal Growth, vol. 1A, North-Holland, Amsterdam, 1993). A consequence of the retrograde solubility is the formation of As precipitates when exceeding the solidus line during the cooling procedure, which is coupled with changes in the intrinsic defect inventory of GaAs (“structural point defects”). A distinction is made between matrix precipitates and decoration precipitates having different size distributions, which are formed by homogenous and heterogenous nucleation, respectively. The size distribution of the decoration precipitates (DP) additionally depends on the dislocation density of the material. The lower the dislocation density, the higher the average size of the precipitates. That is, VGF/VB-GaAs, in particular that having SI properties, has larger, greater DP compared to LEC-GaAs. On the other hand, LEC-GaAs, though having a smaller sized DP, has a relatively high dislocation density of substantially above 1×104 cm−2. Dissolving the precipitates by a holding step in the homogeneity region, and re-precipitating the excessive arsenic by means of a defined cooling process thus represents—considering the distribution and the amount of deposited arsenic—a possibility to control not only the defect inventory, but also of the As precipitates by means of crystal annealing. However, heat treating single crystals of large dimensions poses strict limitations on the realizable heating and cooling rates in view of the physico-thermal properties of GaAs, if thermal strain is to lie below certain limits in favor of a constant dislocation density, or for the avoidance of fractures.
During mechano-chemical polishing of the wafers, the As precipitates cause etch pit-like defects in the surface, which are detectable by light scattering techniques as so-called COPs (Crystal Originated Particles) and are classified depending on their size, and which must meet specifications of the use and the user. The size distribution of the COPs depends, inter alia, on the respective polishing procedure; however, it is basically proportional to the size distribution of the As precipitates. That is, on the average, the COPs are larger in VGF/VB-GaAs than in the LEC material. COPs may disturb epitaxial growth and may cause an unacceptable “roughness” of the stacked layers in the manufacture of device elements. Moreover, it is known that the As precipitates affect the circuit behavior of FETs produced by ion implantation (U.S. Pat. No. 5,219,632).
Besides the common practice of carrying out annealing of the whole crystal (ingot), a heat treatment of single wafers, the so-called wafer annealing, is known. There, different from crystal annealing, use can be made of the fact that, with GaAs (and other III-V compounds), arsenic (i.e., the V component) has a higher vapor pressure than gallium (i.e. the III-component) above the temperature of the congruent evaporation. In this manner, it can be tried, at least in principle, to adjust the composition of GaAs in a surface-near region of the wafer by means of an As partial pressure, which is applied from the outside (for example, by evaporating solid arsenic, or by other means) (see O. Oda, H. Yamamoto, K. Kainosho, T. Imaizumi, H. Okazaki: “Recent developments of III-V materials: annealing and defect control,” Inst. Phys. Conf. Ser. No 135, pp 285-293, 1993).
Another known variant of wafer annealing is heat treatment after ion implantation. It serves for the activation of implanted dopants, wherein a selective As evaporation is suppressed by an As partial pressure corresponding to the activation temperature, or by a diffusion barrier of Si3N4, AlN or another cover layer.
Starting from a 1-step wafer annealing procedure (U.S. Pat. No. 5,219,632), a 2-step (JP 01-153481 A, U.S. Pat. No. 5,047,370) and finally a 3-step procedure (JP 04-215439 A, U.S. Pat. No. 5,137,847) were developed in the wafer annealing for further improvement of the mesoscopic homogeneity.
These developments have in common that, in a first (in U.S. Pat. No. 5,219,632 the only) annealing step at T>1100° C. and t>30 min in a quartz ampoule, the density of the so-called micro defects of typically 5×105 cm−3 in SI LEC GaAs is decreased to ≦5×103 cm−3 under a not further defined As partial pressure, for the avoidance of a selective As evaporation, and by a subsequent cooling to room temperature at a rate of 1-30 K/min. Micro defects are defined as deposits of impurities or As precipitates that can be detected by the known AB etching as oval etch pits on the wafer surface. Preferably, lapped or purity-etched wafers, optionally also in the as-grown status, are used. After double sided etching of the annealed wafers, the second annealing at 750° C.-1100° C. (preferable at 900° C.-1000° C.) is carried out for at least 20 min. Again, it is annealed in a quartz ampoule, but now in a non-oxidizing atmosphere, such as, e.g., N2, H2, Ar or also AsH3, with a not further specified pressure, i.e., non-conservative without As potential and therefore under extracting conditions, or alternatively in a conservative manner with an As partial pressure for suppressing degradation of the surfaces. The indications on the process gas are therefore contradictory. This manner of operation may, however, be provisionally contemplated, to the extent that the wafers are etched, pre-polished and finally polished after the annealing, so that a possibly changed composition in the region close to the surface is of no importance.
In the publications JP 08-255799 A, JP 08-259396 A and JP 09-194300 A, the second annealing in a T range of 800° C.-1000° C. is carried out under an As partial pressure, which is at least 1.4- to 2-fold of the pressure above stoichiometric GaAs at the respective temperature. Thereby, the stoichiometric imbalance and the EL2 concentration associated therewith are increased in a region near the surface. The publications are silent on the behavior of As precipitates during this heat treatment.
In the 3-step wafer annealing described in U.S. Pat. No. 5,137,847 or JP 04-215439 A, a further annealing is carried out at 520-730° C. under As partial pressure. In this document, the 3-step annealing is indicated as being optimal with respect to homogenization and a decrease of micro defects.
The high cooling rate demanded after the first annealing step is disadvantageous and unacceptable, because it leads with high probability to a multiplication of dislocations (slip line formation) based on too high of a thermal strain. This is consistent with the Japanese laid-open patent application JP 2002-274999 A, which limits the heating and cooling rates to ≦200 K/h or ≦100 K/h, as well as with JP 2001-135590 A, which relates to a certain temperature scheme wherein both the heating and the cooling rates are changed depending on the temperature T. However, it was not noticed that critical heating and cooling rates should be different for the avoidance of a multiplication of dislocations for LEC-GaAs and VGF-GaAs, respectively. Furthermore, the amount of material and labor drastically increases concurrent with the number of annealing steps.
In JP 09-199508 A, it is disclosed to stack the GaAs wafers to be annealed one above another, to press them together via an elastic element under a defined pressure, and to anneal them in this manner under a non-oxidizing atmosphere (N2, Ar, H2, AsH2) in a container in a temperature range between 800-1000° C.
JP 05-082527 A discloses a device for annealing wafers in a vertical arrangement. The device consists of 3 azimutally displaced support rods having cuts at defined intervals for receiving the respective wafer. The support rods are fixed to a cone flange. They are formed in a hollow manner, may receive one or more thermo elements and may be supplied by a cooling gas. This device is inserted into a vertically arranged quartz ampoule having a corresponding cone cutting. The ampoule has an extension at its lower extremity for receiving metallic arsenic. The extension projects into a separate heater, the temperature of which controls the As partial pressure in the ampoule and thereby avoids a degradation of the wafers. The wafers are heated by a furnace having several separate heaters, which are controlled by means of an inner thermal element, such that a constant temperature may be maintained over the whole insert length of the wafers. The ampoule may be evacuated. The ampoule having the wafers inserted therein may be closed through a cone cutting, or may be melt sealed as well.
Instead of one wafer for each level, two backside contacted GaAs wafers may also be inserted according to JP 2000-294561.
According to JP 06-302532 A, and likewise in JP 10-287500 A and JP 10-289883 A, the wafers are laid on supports made of heat resistant materials, such as pBN, graphite, silicon, tungsten, molybdenium, and these supports are stacked vertically or horizontally and are inserted into the annealing ampoule in this matter. In the horizontal storage of the wafers on supports, borings between the wafer supports serve for a better exchange with the process gas (see JP 10-321540 A).
EP 0 399 662 A describes a process for annealing semiconductors of the type A3B5 (III-V) and A2B6 (II-VI), wherein the semiconductor having its surface encapsulated by a glass encapsulation film is subjected to a fast thermal annealing (RTA) in order to anneal defects caused by ion implantation. In a treatment device, a cover 12 is provided above a wafer 1 having a thickness of about 500 μm through a spacer ring 11, which typically has a height of 600 to 900 μm, so that a free space of at least 100 μm is formed for allowing the wafer to expand and for enabling a homogeneous heat transfer to the wafer. The encapsulation film intentionally provides a barrier above the wafer surface, such that no (mass) transport is possible between the semiconductor material of the wafer and the free space.